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September 2006 rev 0.4 Low Voltage 1:18 Clock Distribution Chip
Features
* * * * * * * LVPECL Clock Input 2.5V 200pS Skew Maximum Output Frequency of 250MHz @3.3 VCC 32-Lead LQFP and TQFP Packaging Single 3.3V or 2.5V Supply Pin and Function compatible with MPC942P LVCMOS Maximum Outputs Targeted for PentiumII
TM
PCS2I9942P
With low output impedance (12), in both the HIGH and LOW logic states, the output buffers of the PCS2I9942P are ideal for driving series terminated transmission lines. With an output impedance of 12, the PCS2I9942P can drive two series terminated transmission lines from each output. This capability gives the PCS2I9942P an effective fanout of 1:36. The PCS2I9942P provides enough copies of low skew clocks for most high performance synchronous systems. The differential LVPECL inputs of the PCS2I9942P allow the device to interface directly with a LVPECL fanout buffer to build very wide clock fanout trees or to couple to a high frequency clock source. The OE pins will place the outputs into a high impedance state. The OE pin has an internal pullup resistor. The PCS2I9942P is a single supply device. The VCC power pins require either 2.5V or 3.3V. The 32 lead LQFP and TQFP package is chosen to optimize performance, board space and cost of the device. The 32-lead LQFP and TQFP have a 7x7mm2 body size with conservative 0.8mm pin spacing.
Microprocessor Support Output-to-Output
Functional Description
The PCS2I9942P is a 1:18 low voltage clock distribution chip with 2.5V or 3.3V LVCMOS output capabilities. The device is offered in two versions; the PCS2I9942C has an LVCMOS input clock while the PCS2I9942P has a LVPECL input clock. The 18 outputs are 2.5V or 3.3V LVCMOS compatible and feature the drive strength to drive 50 series or parallel terminated transmission lines. With output-to-output skews of 200pS, the PCS2I9942P is ideal as a clock distribution chip for the most demanding of synchronous systems. The 2.5V outputs also make the device ideal for supplying clocks for a high performance Pentium II
TM
microprocessor based design.
* Pentium II is a trademark of Intel Corporation
Block Diagram Q0 PECL_CLK PECL_CLK OE (Int. Pullup) Q1-Q16 Q17
Table 1. Function Table OE
0 1
Output
HIGH IMPEDANCE OUTPUTS ENABLED
PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 * Tel: 408-879-9077 * Fax: 408-879-9018 www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
September 2006 rev 0.4
Pin Diagram
GND Q10 Q11 VCC Q6 Q7 Q8 Q9
PCS2I9942P
24 GND Q5 Q4 Q3 VCC Q2 Q1 Q0 25 26 27 28 29 30 31 32 1
23
22
21
20
19
18
17 16 15 14 VCC Q12 Q13 Q14 GND Q15 Q16 Q17
PCS2I9942P
13 12 11 10 9
2
3
4
5
6
7
8
VCC
PECL_CLK
Table 2. Pin Description Pin #
5 6 3 4 32,31,30,28,27,26,24,23,22,20,19,18,15, 14,13,11,10,9 1,2,12,17,25 7,8,16,21,29
Pin Name
PECL_CLK, PECL_CLK OE NC Q0 - Q17 GND VCC
I/O
Input Input
PECL_CLK
GND
GND
VCC
OE
NC
Type
LVPECL LVCMOS
Function
LVPECL Clock Inputs Output enable/disable (high-impedance tristate) No connect Clock outputs Negative power supply (GND) for I/O and core. Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation
Output Supply Supply
LVCMOS Ground VCC
Table 3. Absolute Maximum Rating1 Symbol
VCC VI IIN TStor Supply Voltage Input Voltage Input Current Storage Temperature Range
Parameter
Min
-0.3 -0.3 -40
Max
3.6 VCC + 0.3 20 125
Unit
V V mA C
Note: 1. These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability.
Low Voltage 1:18 Clock Distribution Chip
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PCS2I9942P
Table 4. DC Characteristics (TA =-40 to +85C, VCC = 2.5V 5%) Symbol
VIH VIL VPP VX VOH VOL IIN CIN CPD ZOUT ICC
Characteristic
Input HIGH Voltage Input LOW Voltage Input Swing PECL_CLK Input Crosspoint PECL_CLK Output HIGH Voltage Output LOW Voltage Input Current Input Capacitance Power Dissipation Capacitance Output Impedance Maximum Quiescent Supply Current
Min
2.0 0.6 VCC-1.0 2.0
Typ
Max
VCC 0.8 1.0 VCC-0.6 0.5 200
Unit
V V V V V V A pF pF
Condition
IOH = -16 mA IOL = 16 mA
4.0 14 12 0.5 5.0
Per Output
mA
Table 5. AC Characteristics (TA =-40 to +85C, VCC = 2.5V 5%) Symbol
Fmax tPLH tPHL tsk(o) tsk(pr) tsk(pr) tr, tf
Characteristic
Maximum Frequency Propagation Delay Propagation Delay Output-to-Output Skew within one bank Part-to-Part Skew 1 Part-to-Part Skew
2
Min
1.8 2.0
Typ
Max
200 4.0 4.3 150 2.2 1.3
Unit
MHz nS nS pS nS pS nS
Condition
Output Rise/Fall Time
0.1
1.0
Note: 1. Across temperature and voltage ranges, includes output skew. 2. For a specific temperature and voltage, includes output skew.
Table 6. DC Characteristics (TA =-40 to +85C, VCC = 3.3V 5%) Symbol
VIH VIL VPP VX VOH VOL IIN CIN CPD ZOUT ICC
Characteristic
Input HIGH Voltage Input LOW Voltage Input Swing PECL.CLK Input Crosspoint PECL_CLK Output HIGH Voltage Output LOW Voltage Input Current Input Capacitance Power Dissipation Capacitance Output Impedance Maximum Quiescent Supply Current
Min
2.4 0.6 VCC-1.0 2.4
Typ
Max
VCC 0.8 1.0 VCC-0.6 0.6 200
Unit
V V V V V V A pF pF
Condition
IOH = -20 mA IOL = 20 mA
4.0 14 12 0.5 5.0
Per Output
mA
Low Voltage 1:18 Clock Distribution Chip
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PCS2I9942P
Table 7. AC Characteristics (TA =-40 to +85C, VCC = 3.3V 5%) Symbol
Fmax tPLH tPHL tsk(o) tsk(pr) tsk(pr) tr, tf
Characteristic
Maximum Frequency Propagation Delay Propagation Delay Output-to-output Skew within one bank Part-to-Part Skew1 Part-to-Part Skew2 Output Rise/Fall Time
Min
1.5 1.5
Typ
Max
250 3.2 3.6 150 1.7 1.0
Unit
MHz nS nS pS nS pS nS
Condition
0.1
1.0
Note: 1. Across temperature and voltage ranges, includes output skew. 2. For a specific temperature and voltage, includes output skew.
Low Voltage 1:18 Clock Distribution Chip
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Power Consumption of the PCS2I9942P and Thermal Management
The PCS2I9942P AC specification is guaranteed for the entire operating frequency range up to 250MHz. The PCS2I9942P power consumption and the associated long-term reliability may decrease the maximum frequency limit, depending on operating conditions such as clock frequency, supply voltage, output loading, ambient temperature, vertical convection and thermal conductivity of package and board. This section describes the impact of these parameters on the junction temperature and gives a guideline to estimate the PCS2I9942P die junction temperature and the associated device reliability.
PCS2I9942P
Where ICCQ is the static current consumption of the PCS2I9942P, CPD is the power dissipation capacitance per output, ()CL represents the external capacitive output load, N is the number of active outputs (N is always 12 in case of the PCS2I9942P). The PCS2I9942P supports driving transmission lines to maintain high signal integrity and tight timing parameters. Any transmission line will hide the lumped capacitive load at the end of the board trace, therefore, CL is zero for controlled transmission line systems and can be eliminated from equation 1. Using parallel termination output termination results in equation 2 for power dissipation. In equation 2, P stands for the number of outputs with a parallel or thevenin termination, VOL, IOL, VOH and IOH are a function of the output termination technique and DCQ is the clock signal duty cycle. If transmission lines are used CL is zero in equation 2 and can be eliminated. In general, the use of controlled transmission line techniques eliminates the impact of the lumped capacitive loads at the end lines and greatly reduces the power dissipation of the device. Equation 3 describes the die junction temperature TJ as a function of the power consumption. Where Rthja is the thermal impedance of the package (junction to ambient) and TA is the ambient temperature. According to Table 8, the junction temperature can be used to estimate the long-term device reliability. Further, combining equation 1 and equation 2 results in a maximum operating frequency for the PCS2I9942P in a series terminated transmission line system, equation 4.
Table 8. Die junction temperature and MTBF Junction temperature (C)
100 110
MTBF (Years)
20.4 9.1
120 4.2 130 2.0 Increased power consumption will increase the die junction temperature and impact the device reliability (MTBF). According to the system-defined tolerable MTBF, the die junction temperature of the PCS2I9942P needs to be controlled and the thermal impedance of the board/package should be optimized.The power dissipated in the PCS2I9942P is represented in equation 1.
PTOT = I CCQ + VCC f CLOCK N C PD + C L VCC M PTOT = VCC I CCQ + VCC f CLOCK N C PD + C L + DC Q I OH (VCC - VOH ) + (1 - DC Q ) I OL VOL M P T J = T A + PTOT Rthja
Equation 1
[
]
Equation 2 Equation 3 Equation 4
f CLOCKMAX =
C PD
1 2 N VCC
T - TA JMAX - (I CCQ VCC ) Rthja
Low Voltage 1:18 Clock Distribution Chip
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TJ,MAX should be selected according to the MTBF system requirements and Table 8. Rthja can be derived from Table 9. The Rthja represent data based on 1S2P boards, using 2S2P boards will result in lower thermal impedance than indicated below.
PCS2I9942P
If the calculated maximum frequency is below 350 MHz, it becomes the upper clock speed limit for the given application conditions. The following eight derating charts describe the safe frequency operation range for the PCS2I9942P. The charts were calculated for a maximum tolerable die junction temperature of 110C (120C), corresponding to an estimated MTBF of 9.1 years (4 years), a supply voltage of 3.3V and series terminated transmission line or capacitive loading. Depending on a given set of these operating conditions and the available device convection a decision on the maximum operating frequency can be made.
Table 9. Thermal package impedance of the 32LQFP Convection, Rthja (1P2S Rthja (2P2S board), C/W board), C/W LFPM
Still air 100 lfpm 200 lfpm 300 lfpm 400 lfpm 500 lfpm 86 76 71 68 66 60 61 56 54 53 52 49
Low Voltage 1:18 Clock Distribution Chip
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Package Information 32-lead TQFP
PCS2I9942P
SECTION A-A
Dimensions Symbol
A A1 A2 D D1 E E1 L L1 T T1 b b1 R0 a e
Inches Min Max
.... 0.0020 0.0374 0.3465 0.2717 0.3465 0.2717 0.0177 0.0035 0.0038 0.0118 0.0118 0.0031 0 0.0472 0.0059 0.0413 0.3622 0.2795 0.3622 0.2795 0.0295 0.0079 0.0062 0.0177 0.0157 0.0079 7
Millimeters Min Max
... 0.05 0.95 8.8 6.9 8.8 6.9 0.45 0.09 0.097 0.30 0.30 0.08 0 0.8 BASE 1.2 0.15 1.05 9.2 7.1 9.2 7.1 0.75 0.2 0.157 0.45 0.40 0.2 7
0.03937 REF
1.00 REF
0.031 BASE
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
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32-lead LQFP
PCS2I9942P
SECTION A-A
Dimensions Symbol
A A1 A2 D D1 E E1 L L1 T T1 b b1 R0 e a
Inches Min Max
.... 0.0020 0.0531 0.3465 0.2717 0.3465 0.2717 0.0177 0.0035 0.0038 0.0118 0.0118 0.0031 0 0.0630 0.0059 0.0571 0.3622 0.2795 0.3622 0.2795 0.0295 0.0079 0.0062 0.0177 0.0157 0.0079 7
Millimeters Min Max
... 0.05 1.35 8.8 6.9 8.8 6.9 0.45 0.09 0.097 0.30 0.30 0.08 0 1.6 0.15 1.45 9.2 7.1 9.2 7.1 0.75 0.2 0.157 0.45 0.40 0.20 7
0.03937 REF
1.00 REF
0.031 BASE
0.8 BASE
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
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Ordering Information Ordering Code
PCS2P9942PG-32-LT PCS2P9942PG-32-LR PCS2P9942PG-32-ET PCS2P9942PG-32-ER PCS2I9942PG-32-LT PCS2I9942PG-32-LR PCS2I9942PG-32-ET PCS2I9942PG-32-ER
PCS2I9942P
Marking
PCS2P9942PGL PCS2P9942PGL PCS2P9942PGE PCS2P9942PGE PCS2I9942PGL PCS2I9942PGL PCS2I9942PGE PCS2I9942PGE
Package Type
32-pin LQFP, Tray, Green 32-pin LQFP, Tape and Reel, Green 32-pin TQFP, Green 32-pin TQFP, Tape and Reel, Green 32-pin LQFP, Tray, Green 32-pin LQFP,Tape and Reel, Green 32-pin TQFP, Green 32-pin TQFP,Tape and Reel, Green
Operating Range
Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial
Device Ordering Information
PCS2I9942PG-32-LR
R = Tape & Reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN DEVICE PIN COUNT U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70
G = GREEN PACKAGE, LEAD FREE, and RoHS
PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved
PulseCore Semiconductor Mixed Signal Product
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
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PCS2I9942P
PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com
Copyright (c) PulseCore Semiconductor All Rights Reserved Preliminary Information Part Number: PCS2I9942P Document Version: 0.4
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003
(c) Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore's best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore's Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore's Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use.
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
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